2013.05.14.18:43:55 |
Datasheet |
Overview
Memory Map
sfp0_mac_to_64
data_format_adapter v12.1
Parameters
generationLanguage |
VERILOG |
inBitsPerSymbol |
8 |
inChannelWidth |
0 |
inErrorDescriptor |
FCS_ERROR |
inErrorWidth |
1 |
inMaxChannel |
0 |
inReadyLatency |
0 |
inSymbolsPerBeat |
4 |
inUseEmpty |
false |
inUseEmptyPort |
YES |
inUsePackets |
true |
inUseReady |
true |
moduleName |
|
outSymbolsPerBeat |
8 |
outUseEmpty |
false |
outUseEmptyPort |
YES |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
sfp0_rx_dc_fifo
altera_avalon_dc_fifo v12.1
Parameters
SYMBOLS_PER_BEAT |
8 |
BITS_PER_SYMBOL |
8 |
FIFO_DEPTH |
16 |
CHANNEL_WIDTH |
0 |
ERROR_WIDTH |
1 |
USE_PACKETS |
1 |
USE_IN_FILL_LEVEL |
0 |
USE_OUT_FILL_LEVEL |
0 |
WR_SYNC_DEPTH |
2 |
RD_SYNC_DEPTH |
2 |
ENABLE_EXPLICIT_MAXCHANNEL |
false |
EXPLICIT_MAXCHANNEL |
0 |
AUTO_DEVICE_FAMILY |
STRATIXV |
deviceFamily |
Stratix V |
generateLegacySim |
false |
|
Software Assignments(none) |
nic0_64_to_mac
data_format_adapter v12.1
Parameters
generationLanguage |
VERILOG |
inBitsPerSymbol |
8 |
inChannelWidth |
0 |
inErrorDescriptor |
|
inErrorWidth |
1 |
inMaxChannel |
0 |
inReadyLatency |
0 |
inSymbolsPerBeat |
8 |
inUseEmpty |
false |
inUseEmptyPort |
YES |
inUsePackets |
true |
inUseReady |
true |
moduleName |
|
outSymbolsPerBeat |
4 |
outUseEmpty |
false |
outUseEmptyPort |
YES |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
nic0_tx_dc_fifo
altera_avalon_dc_fifo v12.1
Parameters
SYMBOLS_PER_BEAT |
8 |
BITS_PER_SYMBOL |
8 |
FIFO_DEPTH |
16 |
CHANNEL_WIDTH |
0 |
ERROR_WIDTH |
1 |
USE_PACKETS |
1 |
USE_IN_FILL_LEVEL |
0 |
USE_OUT_FILL_LEVEL |
0 |
WR_SYNC_DEPTH |
2 |
RD_SYNC_DEPTH |
2 |
ENABLE_EXPLICIT_MAXCHANNEL |
false |
EXPLICIT_MAXCHANNEL |
0 |
AUTO_DEVICE_FAMILY |
STRATIXV |
deviceFamily |
Stratix V |
generateLegacySim |
false |
|
Software Assignments(none) |
sfp0_64_to_mac
data_format_adapter v12.1
Parameters
generationLanguage |
VERILOG |
inBitsPerSymbol |
8 |
inChannelWidth |
0 |
inErrorDescriptor |
|
inErrorWidth |
1 |
inMaxChannel |
0 |
inReadyLatency |
0 |
inSymbolsPerBeat |
8 |
inUseEmpty |
false |
inUseEmptyPort |
YES |
inUsePackets |
true |
inUseReady |
true |
moduleName |
|
outSymbolsPerBeat |
4 |
outUseEmpty |
false |
outUseEmptyPort |
YES |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
sfp0_tx_dc_fifo
altera_avalon_dc_fifo v12.1
Parameters
SYMBOLS_PER_BEAT |
8 |
BITS_PER_SYMBOL |
8 |
FIFO_DEPTH |
16 |
CHANNEL_WIDTH |
0 |
ERROR_WIDTH |
1 |
USE_PACKETS |
1 |
USE_IN_FILL_LEVEL |
0 |
USE_OUT_FILL_LEVEL |
0 |
WR_SYNC_DEPTH |
2 |
RD_SYNC_DEPTH |
2 |
ENABLE_EXPLICIT_MAXCHANNEL |
false |
EXPLICIT_MAXCHANNEL |
0 |
AUTO_DEVICE_FAMILY |
STRATIXV |
deviceFamily |
Stratix V |
generateLegacySim |
false |
|
Software Assignments(none) |
board_services_connections
application_demux_wiring v1.0
nic0_64_to_mac
|
out |
board_services_connections |
nic0_tx |
|
sfp0_64_to_mac
|
out |
sfp1_tx |
|
|
sfp_312_5_clk |
sfp0_rx_dc_fifo
|
|
|
in_clk |
|
|
sfp_312_5_reset_n |
|
|
in_clk_reset |
|
|
clk_200 |
|
|
out_clk |
|
|
async_reset_n |
|
|
out_clk_reset |
|
|
|
async_reset_n |
sfp0_mac_to_64
|
|
|
reset |
|
|
sfp_312_5_clk |
|
|
clk |
|
|
sfp0_rx |
|
|
in |
|
|
|
nic_312_5_clk |
nic0_64_to_mac
|
|
|
clk |
|
|
nic_312_5_reset_n |
|
|
reset |
|
|
|
nic_312_5_clk |
nic0_tx_dc_fifo
|
|
|
out_clk |
|
|
clk_200 |
|
|
in_clk |
|
|
async_reset_n |
|
|
in_clk_reset |
|
|
nic_312_5_reset_n |
|
|
out_clk_reset |
|
|
|
clk_200 |
sfp0_tx_dc_fifo
|
|
|
in_clk |
|
|
async_reset_n |
|
|
in_clk_reset |
|
|
clk_200_reset_n |
|
|
in_clk_reset |
|
|
sfp_312_5_clk |
|
|
out_clk |
|
|
sfp_312_5_reset_n |
|
|
out_clk_reset |
|
|
|
sfp_312_5_clk |
sfp0_64_to_mac
|
|
|
clk |
|
|
sfp_312_5_reset_n |
|
|
reset |
|
|
|
clk_200 |
killswitch_t1r0
|
|
|
clock |
|
|
clk_200_reset_n |
|
|
reset |
Parameters
MUX_SIZE_IN |
500 |
MUX_SIZE_OUT |
500 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
killswitch_t1r0
killswitch v3.4
Parameters
id_length |
80 |
statistic_width |
96 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
generation took 0.01 seconds |
rendering took 0.09 seconds |