Sample behavioral waveforms for design file ddr_pll_cycloneii.vhd

The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design ddr_pll_cycloneii.vhd. The design ddr_pll_cycloneii.vhd has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps.