Selected Publications

"Self-Timed Carry-Lookahead Adders" [pdf]
F.-C. Cheng, S.H. Unger and M. Theobald
IEEE Transactions on Computers, Special Issue on Computer Arithmetic, Volume 49, Issue 7, July 2000, Pp. 659-672.

"A Low-Latency FIFO for Mixed-Clock Systems" [pdf][ps]
T. Chelcea and S.M. Nowick
Proceedings of the IEEE Workshop on VLSI (WVLSI), 2000, Pp. 119-126.

"Low-Latency Asynchronous FIFO's Using Token Rings" [pdf] [ps]
T. Chelcea and S.M. Nowick
Proceedings of the Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'00), 2000, Pp. 210-220.

"Synthesis for Logical Initializability of Synchronous Finite-State Machines" [pdf] [ps]
M. Singh and S.M. Nowick
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 8, Oct. 2000, Pp. 542-557.

"Fine-Grain Pipelined Asynchronous Adders for High-Speed DSP Applications" [pdf] [ps]
M. Singh and S.M. Nowick
Proceedings of the IEEE Computer Society Workshop on VLSI (WVLSI), 2000, Pp. 111-118.

"High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths" [pdf] [ps]
M. Singh and S.M. Nowick
Proceedings of the Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'00), 2000, Pp. 198-209.  Best Paper Award.

"A Power-Efficient Duplex Communication System" [pdf] [ps]
S.B. Furber, A. Efthymiou, and M. Singh
Workshop on Asynchronous Interfaces: Tools, Techniques and Implementations (AINT-2000), Delft, The Netherlands, July 2000.

"Scanning the Technology: Applications of Asynchronous Circuits" [pdf] [ps]
C.H. Van Berkel, M.B. Josephs, and S.M. Nowick
Proceedings of the IEEE, Volume 87, Issue 2, Feb. 1999, Pp. 223-233.

"OPTIMISTA: State Minimization of Asynchronous FSMs for Optimum Output Logic" [pdf] [ps]
R.M. Fuhrer and S.M. Nowick
Proceeding of the International Conference on Computer-aided design, 1999, Pp. 7-13. 

"Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools" [pdf] [ps]
R.M. Fuhrer
PhD Thesis, Computer Science Department, Columbia University, 1999.

"MINIMALIST: An Environment for the Synthesis, Verification and Testability of Burst-Mode Asynchronous Machines" [pdf] [ps]
R.M. Fuhrer, S.M. Nowick, M. Theobald, N.K. Jha, B. Lin, and L. Plana
Technical Report CUCS-020-99, Computer Science Department, Columbia University, July 1999.

"Fast Heuristic and Exact Algorithms for Two-Level Hazard-Free Logic Minimization" [pdf]
M. Theobald and S. Nowick
IEEE Transactions on Computer-Aided Design, Volume 11, Nov. 1998, Pp. 1130-1147.

"An Implicit Method for Hazard-Free Two-Level Logic Minimization" [pdf]
M. Theobald and S. Nowick
IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'98), March 1998, Pp. 58-69.  Best Paper Finalist.

"A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors" [pdf] [ps]
R. Benes, S.M. Nowick, and A. Wolfe
Proceedings of the Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'98), March 1998, Pp. 43-56.

"Synthesis of Low-Power Asynchronous Circuits in a Specified Environment" [pdf]
S.M. Nowick and M. Theobald
International Symposium on Low Power Electronics and Design, August 1997, Pp. 92-95.

"A High-Speed Asynchronous Decompression Circuit for Embedded Processors" [pdf] [ps]
M. Benes, A. Wolfe, and S.M. Nowick
Proceedings of the Seventeenth Conference on Advanced Research in VLSI, 1997, Pp. 219-236.

"Synthesis of Asynchronous Circuits for Stuck-at and Robust Path Delay Fault Testability" [pdf] [ps]
S.M. Nowick, N.K. Jha, and F.-C. Cheng
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 16, Issue 12, Dec. 1997, Pp. 1514-1521.

"Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders" [pdf] [ps]
S.M. Nowick, K.Y. Yun, P.A. Beerel, and A.E. Dooply
Proceedings of the Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'97), 1997, Pp. 210-223.

"Synthesis for Logical Initializability of Synchronous Finite State Machines" [pdf] [ps]
M. Singh and S.M. Nowick
Proceedings of the Tenth International Conference on VLSI Design, 1997, Pp. 76-80.

"An Introduction to Asynchronous Circuit Design" [pdf] [ps]
A. Davis and S.M. Nowick
Technical Report UUCS-97-013, Computer Science Department, University of Utah, Sep. 1997.

"Fast OFDD-Based Minimization of Fixed Polarity Reed-Muller Expressions" [pdf]
R. Drechsler, M. Theobald, and B. Becker
IEEE Transactions on Computers, Volume 45, Issue 11, November 1996, Pp. 1294-1299.

"Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic" [pdf]
M. Theobald, S.M. Nowick, T. Wu
Proceedings of the 33rd Annual Design Automation Conference (DAC), 1996, Pp. 71-76.

"Synthesis-for-Initializability of Asynchronous Sequential Machines" [pdf] [ps]
M. Singh and S.M. Nowick
Proceedings of the International Test Conference, 1996, Pp. 232-241.

"State Assignment for Initializability of Synchronous Finite State Machines" [pdf] [ps]
M. Singh and S.M. Nowick
International Test Synthesis Workshop, Santa Barbara, CA, May 1996.

"Symbolic Hazard-Free Minimization and Encoding of Asynchronous Finite State Machines" [pdf] [ps]
R.M. Fuhrer, B. Lin, and S.M. Nowick
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD-95), 1995, Pp. 604-611.

"Exact Two-Level Minimization of Hazard-Free Logic with Multiple-Input Changes" [pdf] [ps]
S.M. Nowick and D.L. Dill
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 14, Issue 8, Aug. 1995, Pp. 986-997.

"Automatic Synthesis of Burst-Mode Asynchronous Controllers" [pdf] [ps]
S.M. Nowick
Technical Reporst CSL-TR-95-686, Computer Science Department, Stanford University, Dec. 1995.

"Fast OFDD based Minimization of Fixed Polarity Reed-Muller Expressions" [pdf]
R. Drechsler, M. Theobald, and B. Becker
European Design Automation Conference (Euro-DAC), Sep. 1994, Pp. 2-7.